1. Field of the Invention
The present invention relates to a semiconductor apparatus, including an electrostatic discharge protection circuit (hereinafter referred to as an “ESD protection circuit”) for protecting internal circuits from electrostatic discharge (hereinafter simply referred to as “ESD”) caused by too much electrostatic input through an external circuit, and more particularly, to a semiconductor apparatus including a radiator for diffusing the heat generated in the ESD protection circuit.
2. Description of the Background Art
To understand an example of an ESD protection circuit for a semiconductor apparatus, an equivalent circuit of an ESD protection circuit is illustrated in FIG. 15. As shown, ESD protection circuit 90 is usually provided between input terminal 91 (hereinafter frequently referred to as “bonding pad 91”) on a semiconductor chip, and output terminal 93 for connection to an internal circuit (not shown). Bonding pad 91 and an internal circuit are coupled through input wiring 92, and one terminal of ESD protection circuit 90 is connected to input wiring 92. The other terminal of ESD protection circuit 90 is coupled to the grounding node. In FIG. 15, ESD protection circuit 90 is constructed by an n-channel metal oxide semiconductor (NMOS) transistor, e.g., NMOS field-effect transistor (NMOSFET) element. Thus, gate terminal G of the NMOSFET is directly connected to source terminal S of the NMOSFET in order to use the protection element as a diode. Drain terminal D of the NMOSFET is connected to input wiring 92, and source terminal S is grounded.
FIG. 16 illustrates a cross-sectional view of an example configuration of the EDS protection element of the NMOSFET portion of ESD protection circuit 90, shown in FIG. 15. In p-type semiconductor substrate 1, drain area 3 and source area 4 are formed as an n-type diffused layer between element separating areas 2. Insulating film 5 is provided on a channel area covering the area between drain area 3 and source area 4. Gate electrode 6 is formed on insulating film 5. Interlayer insulating film 7 covers p-type semiconductor substrate 1. Two contact holes are provided in interlayer insulating film 7 at respective positions of each surface of drain area 3 and source area 4. Two plug-shaped contacts 8 and 9, hereinafter, sometimes referred to as contact plugs, are embedded in each of the two contact holes. At a position corresponding to each of two plugs 8 and 9, drain wiring 10 and source wiring 11 are connected, respectively. Drain wiring 10 and source wiring 11 are formed by a first layer metal wiring, for example, copper (Cu) or aluminum (Al). On each surface portion of drain area 3 and source area 4, metal silicide layer 12 is provided, so as to contact to each of plugs 8 and 9, respectively.
Eventually, when too much voltage input is supplied to the internal circuit, a breakdown of the EDS protection element will likely occur at the level of individual elements in the EDS protection element, such as at a gate element or a resistance element in a metal-oxide semiconductor field-effect transistor (MOSFET). Such a breakdown of protection element 90 occurs due to layer fusing caused by the joule heat generated in the layers, when too much current flows into the EDS protection circuit.
Conventionally, it has been proposed to increase a resistance value of the n-type diffused layer 22, in order to increase tolerance against such a situation when too much voltage is input for the protection of MOSFET element 90 itself. For example, it has been proposed to expand the width of n-type diffused layer 22 on gate electrode 6, along a parallel direction. Also, it has been proposed to expand each space between gate electrode 6 and respective contacts 8 and 9 provided on n-type diffused layer 22.
However, recent advances in technology for a semiconductor apparatus have achieved a fine process for reducing a wiring width, and a thinness of a wiring film. By reducing wiring delays, or achieving a low value of permittivity of an interlayer insulating film, it becomes possible to achieve a high-performance semiconductor device. Further, it has recently been proposed to construct wiring layers in a stacked multiple-layer form. In order to achieve these recent advances in technologies, it has been considered to take some measures to protect the wiring layers of the stacked multiple-layer, since such a stacked multiple-layer form inevitably reduces radiation effects of the wiring layers. Thus, one needs to provide a surge current path for the ESD protection circuit.
To protect wiring layers used as the surge current path in the ESD protection circuit, it has been proposed to simply expand a width of the wiring layer, so as to increase tolerance against excessive voltage input. However, this measure is insufficient for protecting the wiring layer in the ESD protection circuit, since excessive current flow due to the excessive voltage input into the ESD protection circuit easily exceeds over many tens to hundreds times of a permitted current density (defined by electromigration (ED)) in the wiring layer acting as a surge current path. Consequently, the generated heat that is caused by such a large surge current may easily fuse the wiring layers for connecting to the internal circuit.
FIG. 17 displays a relationship between an amount of current flowing into a metal wiring layer and an increase in temperature caused by the heat generated in the wiring layers. A ratio of a contact surface (CS) to a diffused layer surface is used as a parameter for the relationship between the current and the temperature increase. Thus, in FIG. 17, the black-circle line shows a 0.1% size ratio of metal wiring layer contact surface to the diffused layer in the substrate. The black-rectangular line depicts a change in the ratio to 1%, and the black-triangle line depicts a change in the ratio to 10%. It is understood that an increase amount of the generated heat (shown on the ordinate in FIG. 17 as the “temperature increase”) reduces in accordance with an increase of the size ratio of the contact plug. Thus, the generated heat is absorbed into the semiconductor substrate, such as a silicon substrate, through the contact surface (CS) 22, shown in FIG. 16. Accordingly, the temperature increase of the metal wiring layer cannot be reduced according to conventional techniques.
Japanese Patent Application Publication No. 5-3286 has proposed to form a tungsten film radiator contacted to the drain area of the MOS transistor in the input protection circuit, in order to increase the radiation effect for the generated joule heat at the drain area. However, this proposal is also insufficient for protecting a wiring layer as a surge current path from an excessive voltage input into the ESD protection circuit. Thus, development of a new measurement for sufficiently radiating the heat generated in the wiring layer used as a surge current path in the ESD protection circuit has been sought.